Integrated circuits typically involve active circuits that draw spikes of current from a local power supply line or bus. One example of an active circuit that may draw such a spike of current is a digital logic element disposed on an integrated circuit. The digital logic element has a VCC power lead that is coupled by a power (VCC) supply line or bus to a power VCC terminal or pad of the integrated circuit. If, for example, the digital logic element is disposed in the center of the integrated circuit, then the power supply line can be quite long and may have significant resistance and inductance.
When a signal on an input lead of the digital logic element switches from one digital logic level to another digital logic level, the digital logic element may draw a spike of current from the power supply line. This spike of current can include a crossover current that passes from the VCC power lead of the digital logic element through the digital logic element and to a ground lead of the digital logic element. This spike of current can also include a switching current needed to supply electrical charge to the load of the digital logic element such that the voltage on the output of the digital logic element can transition from one digital logic voltage to another.
If the power supply line had no resistance or inductance, then the spike of current could be supplied to the digital logic element through the supply line without a significant drop in the voltage on the VCC power lead of the digital logic element. However, because some resistance and inductance is inherently associated with the power supply line, the voltage on the VCC power lead of the digital logic element may drop momentarily when the digital logic element switches from one digital logic level to another.
Such a voltage drop can have undesirable consequences. For example, where the signal output from the digital logic element is to switch from a digital logic low to a digital logic high, the voltage on the VCC power lead of the digital logic element might momentarily dip to a level that is not recognized as a digital logic high. This voltage dip can delay the transition of the signal and can cause other problems.
One technique used to prevent undesirable dips in supply voltage to active devices is to provide “bypass capacitors” close to the active devices. When an active device draws a spike of current, much of this current is supplied by a local bypass capacitor, thereby reducing the magnitude of the current spike pulled through the VCC power supply line. By reducing the magnitude of the current spike pulled through the supply line, the magnitude of the associated voltage drop at the power supply lead of the active device is reduced as well.
U.S. Pat. No. 6,144,225 describes a technique whereby an integrated metal plate bypass capacitor is fashioned from the upper layers of metallization above active elements on an integrated circuit. When one of the active elements of the integrated circuit draws a spike of supply current, at least some of that spike of current is provided by the overlying integrated metal plate bypass capacitor. Employing this technique may consume undesirable amounts of metal routing resources in the upper layers of metallization.
U.S. Pat. No. 6,271,059 describes another technique involving a connector that contains active circuits and which may also include decoupling capacitors. Metallized stub terminals laterally disposed with respect to the active circuits and decoupling capacitors on the connector couple the connector to an overlying integrated circuit chip. Due to the metallized stub terminals, the decoupling capacitors are disposed a distance from any active circuits on the overlying integrated circuit that might be receiving bypass current from the connector. This distance may introduce unwanted resistance and/or inductance in the attendant connection from the decoupling capacitor to the integrated circuit.
U.S. Pat. No. 6,410,431 discloses another technique that uses chip-to-chip connectors to mount multiple smaller decoupling capacitors on the front and back surfaces of relatively larger chips. The mounting of multiple smaller decoupling capacitors in this fashion is seen to be somewhat impractical.
An improved and practical circuit configuration and method is sought for more directly providing bypass current to the active circuits that need the bypass current.